SPU channel optimization (#1675)
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@@ -132,7 +132,7 @@ bool spursDma(SPUThread& spu, u32 cmd, u64 ea, u32 lsa, u32 size, u32 tag)
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{
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u32 rv;
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rv = spu.get_ch_value(MFC_RdAtomicStat);
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spu.get_ch_value(MFC_RdAtomicStat, rv);
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auto success = rv ? true : false;
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success = cmd == MFC_PUTLLC_CMD ? !success : success;
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return success;
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@@ -146,7 +146,7 @@ u32 spursDmaGetCompletionStatus(SPUThread& spu, u32 tagMask)
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{
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spu.set_ch_value(MFC_WrTagMask, tagMask);
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spu.set_ch_value(MFC_WrTagUpdate, MFC_TAG_UPDATE_IMMEDIATE);
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return spu.get_ch_value(MFC_RdTagStat);
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u32 rv; spu.get_ch_value(MFC_RdTagStat, rv); return rv;
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}
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// Wait for DMA operations to complete
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@@ -154,7 +154,7 @@ u32 spursDmaWaitForCompletion(SPUThread& spu, u32 tagMask, bool waitForAll)
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{
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spu.set_ch_value(MFC_WrTagMask, tagMask);
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spu.set_ch_value(MFC_WrTagUpdate, waitForAll ? MFC_TAG_UPDATE_ALL : MFC_TAG_UPDATE_ANY);
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return spu.get_ch_value(MFC_RdTagStat);
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u32 rv; spu.get_ch_value(MFC_RdTagStat, rv); return rv;
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}
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// Halt the SPU
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@@ -163,6 +163,89 @@ void spursHalt(SPUThread& spu)
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spu.halt();
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}
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void sys_spu_thread_exit(SPUThread& spu, s32 status)
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{
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u32 _v;
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// Cancel any pending status update requests
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spu.set_ch_value(MFC_WrTagUpdate, 0);
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while (spu.get_ch_count(MFC_RdTagStat) != 1);
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spu.get_ch_value(MFC_RdTagStat, _v);
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// Wait for all pending DMA operations to complete
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spu.set_ch_value(MFC_WrTagMask, 0xFFFFFFFF);
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spu.set_ch_value(MFC_WrTagUpdate, MFC_TAG_UPDATE_ALL);
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spu.get_ch_value(MFC_RdTagStat, _v);
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spu.set_ch_value(SPU_WrOutMbox, status);
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spu.stop_and_signal(0x102);
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}
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void sys_spu_thread_group_exit(SPUThread& spu, s32 status)
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{
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u32 _v;
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// Cancel any pending status update requests
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spu.set_ch_value(MFC_WrTagUpdate, 0);
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while (spu.get_ch_count(MFC_RdTagStat) != 1);
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spu.get_ch_value(MFC_RdTagStat, _v);
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// Wait for all pending DMA operations to complete
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spu.set_ch_value(MFC_WrTagMask, 0xFFFFFFFF);
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spu.set_ch_value(MFC_WrTagUpdate, MFC_TAG_UPDATE_ALL);
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spu.get_ch_value(MFC_RdTagStat, _v);
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spu.set_ch_value(SPU_WrOutMbox, status);
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spu.stop_and_signal(0x101);
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}
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s32 sys_spu_thread_send_event(SPUThread& spu, u8 spup, u32 data0, u32 data1)
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{
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if (spup > 0x3F)
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{
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return CELL_EINVAL;
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}
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if (spu.get_ch_count(SPU_RdInMbox))
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{
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return CELL_EBUSY;
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}
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spu.set_ch_value(SPU_WrOutMbox, data1);
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spu.set_ch_value(SPU_WrOutIntrMbox, (spup << 24) | (data0 & 0x00FFFFFF));
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spu.get_ch_value(SPU_RdInMbox, data0);
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return data0;
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}
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s32 sys_spu_thread_switch_system_module(SPUThread& spu, u32 status)
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{
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if (spu.get_ch_count(SPU_RdInMbox))
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{
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return CELL_EBUSY;
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}
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u32 result;
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// Cancel any pending status update requests
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spu.set_ch_value(MFC_WrTagUpdate, 0);
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while (spu.get_ch_count(MFC_RdTagStat) != 1);
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spu.get_ch_value(MFC_RdTagStat, result);
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// Wait for all pending DMA operations to complete
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spu.set_ch_value(MFC_WrTagMask, 0xFFFFFFFF);
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spu.set_ch_value(MFC_WrTagUpdate, MFC_TAG_UPDATE_ALL);
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spu.get_ch_value(MFC_RdTagStat, result);
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do
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{
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spu.set_ch_value(SPU_WrOutMbox, status);
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spu.stop_and_signal(0x120);
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spu.get_ch_value(SPU_RdInMbox, result);
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}
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while (result == CELL_EBUSY);
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return result;
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}
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//----------------------------------------------------------------------------
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// SPURS kernel functions
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//----------------------------------------------------------------------------
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@@ -1643,8 +1726,9 @@ s32 spursTasketSaveTaskContext(SPUThread& spu)
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v128 r;
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spu.fpscr.Read(r);
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ctxt->savedContextFpscr = r;
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ctxt->savedSpuWriteEventMask = spu.get_ch_value(SPU_RdEventMask);
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ctxt->savedWriteTagGroupQueryMask = spu.get_ch_value(MFC_RdTagMask);
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u32 r32;
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spu.get_ch_value(SPU_RdEventMask, r32); ctxt->savedSpuWriteEventMask = r32;
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spu.get_ch_value(MFC_RdTagMask, r32); ctxt->savedWriteTagGroupQueryMask = r32;
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// Store the processor context
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const u32 contextSaveStorage = vm::cast(taskInfo->context_save_storage_and_alloc_ls_blocks & -0x80, HERE);
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