Add missing LSWX and STSWX instructions.

rpcs3/Emu/Cell/PPUDisAsm.h

@@ -1629,6 +1629,10 @@ private:
 	{
 		DisAsm_R3("ldbrx", rd, ra, rb);
 	}
+	void LSWX(u32 rd, u32 ra, u32 rb)
+	{
+		DisAsm_R3("lswx", rd, ra, rb);
+	}
 	void LWBRX(u32 rd, u32 ra, u32 rb)
 	{
 		DisAsm_R3("lwbrx", rd, ra, rb);
@@ -1673,6 +1677,10 @@ private:
 	{
 		DisAsm_V1_R2("stvlx", vs, ra, rb);
 	}
+	void STSWX(u32 rs, u32 ra, u32 rb)
+	{
+		DisAsm_R3("swswx", rs, ra, rb);
+	}
 	void STWBRX(u32 rs, u32 ra, u32 rb)
 	{
 		DisAsm_R3("stwbrx", rs, ra, rb);

rpcs3/Emu/Cell/PPUInstrTable.h

@@ -534,6 +534,7 @@ namespace PPU_instr
 	/*0x1eb*/bind_instr(g1f_list, DIVW, RD, RA, RB, OE, RC);
 	/*0x207*/bind_instr(g1f_list, LVLX, VD, RA, RB);
 	/*0x214*/bind_instr(g1f_list, LDBRX, RD, RA, RB);
+	/*0x215*/bind_instr(g1f_list, LSWX, RD, RA, RB);
 	/*0x216*/bind_instr(g1f_list, LWBRX, RD, RA, RB);
 	/*0x217*/bind_instr(g1f_list, LFSX, FRD, RA, RB);
 	/*0x218*/bind_instr(g1f_list, SRW, RA, RS, RB, RC);
@@ -545,6 +546,7 @@ namespace PPU_instr
 	/*0x257*/bind_instr(g1f_list, LFDX, FRD, RA, RB);
 	/*0x277*/bind_instr(g1f_list, LFDUX, FRD, RA, RB);
 	/*0x287*/bind_instr(g1f_list, STVLX, VS, RA, RB);
+	/*0x296*/bind_instr(g1f_list, STSWX, RS, RA, RB);
 	/*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB);
 	/*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB);
 	/*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB);

rpcs3/Emu/Cell/PPUInterpreter.h

@@ -3016,6 +3016,10 @@ private:
 	{
 		CPU.GPR[rd] = (u64&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]];
 	}
+	void LSWX(u32 rd, u32 ra, u32 rb)
+	{
+		UNK("lswx");
+	}
 	void LWBRX(u32 rd, u32 ra, u32 rb)
 	{
 		CPU.GPR[rd] = (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]];
@@ -3106,6 +3110,10 @@ private:
 
 		Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb);
 	}
+	void STSWX(u32 rs, u32 ra, u32 rb)
+	{
+		UNK("stwsx");
+	}
 	void STWBRX(u32 rs, u32 ra, u32 rb)
 	{
 		(u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs];

rpcs3/Emu/Cell/PPUOpcodes.h

@@ -345,6 +345,7 @@ namespace PPU_opcodes
 		DIVW   = 0x1eb,
 		LVLX   = 0x207, //Load Vector Left Indexed
 		LDBRX  = 0x214,
+		LSWX   = 0x215,
 		LWBRX  = 0x216,
 		LFSX   = 0x217,
 		SRW    = 0x218,
@@ -356,6 +357,7 @@ namespace PPU_opcodes
 		LFDX   = 0x257,
 		LFDUX  = 0x277,
 		STVLX  = 0x287, //Store Vector Left Indexed
+		STSWX  = 0x295,
 		STWBRX = 0x296,
 		STFSX  = 0x297,
 		STVRX  = 0x2a7, //Store Vector Right Indexed
@@ -741,6 +743,7 @@ public:
 	virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
 	virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0;
 	virtual void LDBRX(u32 rd, u32 ra, u32 rb) = 0;
+	virtual void LSWX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0;
 	virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
@@ -752,6 +755,7 @@ public:
 	virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0;
 	virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0;
 	virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0;
+	virtual void STSWX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;