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TSX/PPU: fix conditional store regression

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Nekotekina
2021-12-17 21:48:01 +03:00
parent 18f59d3be8
commit 3e1e1a683c
2 changed files with 3 additions and 4 deletions
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rpcs3/Emu/Cell/PPUThread.cpp
+1 -2
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@@ -2339,7 +2339,7 @@ static bool ppu_store_reservation(ppu_thread& ppu, u32 addr, u64 reg_value)
// Aligned 8-byte reservations will be used here // Aligned 8-byte reservations will be used here
addr &= -8; addr &= -8;
const u64 lock_bits = g_cfg.core.spu_accurate_dma ? vm::rsrv_unique_lock : 1; const u64 lock_bits = vm::rsrv_unique_lock;
auto [_oldd, _ok] = res.fetch_op([&](u64& r) auto [_oldd, _ok] = res.fetch_op([&](u64& r)
{ {
@@ -2348,7 +2348,6 @@ static bool ppu_store_reservation(ppu_thread& ppu, u32 addr, u64 reg_value)
return false; return false;
} }
// Despite using shared lock, doesn't allow other shared locks (TODO)
r += lock_bits; r += lock_bits;
return true; return true;
}); });